SuperH


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The SuperH (or SH) is brandname of a certain microcontroller and microprocessor architecture. The SuperH is fundamentally a 32-bit load/store RISC architecture found in a large number of embedded systems.

Contents

History

The SuperH processor core family was first developed by Hitachi in the early 1990s. Many microcontrollers and microprocessors were based on this architecture. Hitachi was developing a complete set of instruction set upward compatible CPU cores. Originally, the SH-1 and the SH-2 were used in the Sega Saturn and Sega 32X and then later in many other microcontrollers used in many other embedded applications. These cores use a 16-bit instruction set, though register length and data paths are 32-bit, which gave it an excellent code density. At the time, memory was very expensive.

A few years later, the SH-3 core was added to this family of CPU cores; new features included another interrupt concept, a memory management unit (MMU) and a modified cache concept. The SH-3 core also got a DSP extension, then called SH-3-DSP core. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.

For the Sega Dreamcast, Hitachi was then developing the SH-4 architecture. This was a massive extension of the previous cores. Superscalar (2-way) instruction execution and a parallel vector floating point unit were the highlights of this architecture. This CPU core was then also used in many chipsets for embedded applications requiring a very high performance. SH-4 based standard chips were introduced around 1998.

A bit later, Hitachi and ST Microelectronics formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. SuperH, Inc. sold the IP of these CPU cores to Renesas Technology.

The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; recent ARM processors have a 16-bit Thumb mode, and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.

After that, the evolution of the SuperH architecture still continued. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.

Today, the SuperH CPU cores, architecture and products are with Renesas Technology, a merger of the Hitachi and Mitsubishi semiconductor groups, and the architecture is consolidated around the SH2, SH2A, SH3, SH4 and SH4A platforms giving a scalable family from a small low cost solution through numerous options up to the highest possible performance.

See further details under Renesas.

Models

Hitachi SH-3 CPU

The family of SuperH CPU cores include:

  • SH-1 - used in microcontrollers for deeply embedded applications (CD-ROM drives, major appliances, etc)
  • SH-2 - used in microcontrollers with higher performance requirements, also used in automotive such as engine control units or in networking applications, and also in video game consoles, like the Sega Saturn. The SH2 has also found home in a great many motor control applications.
  • SH-2A - The SH2A core is an extension of the SH2 core including a few extra instructions but most importantly moving to a superscalar architecture (which means it executes 2 instructions in a single cycle) and two 5 stage pipelines. It also incorporates 15 register banks to facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation
  • SH-DSP - initially developed for the mobile phone market, used later in many consumer applications requiring DSP performance for JPEG compression etc
  • SH-3 - used for mobile and handheld applications such as the Jornada, strong in Windows CE applications and market for many years in the car navigation market
  • SH-3-DSP - used mainly in multimedia terminals and networking applications, also in printers and fax machines
  • SH-4 - used whenever high performance is required such as car multimedia terminals, video game consoles, or set-top boxes
  • SH-5 - used in high-end multimedia applications
  • SH-X - mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones
  • SH-Mobile - SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI, this is a solution to ease system development and realise significant performance improvement.

The SuperH cores are supported worldwide by many RTOS and tool vendors.

SH2

The SH2 is a modern-day high-performance 32bit RISC architecture, it features many (16) general purpose registers, ideal for programs written in C.

It has a 16bit fixed length instructions for high code density, features a hardware Multiply-Accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.

The SH2 has a cache on all ROM-less devices.

It also features many nice little features such as vector-base-register, global-base-register and a procedure register.

Today the SH2 family stretches from 32k of on board flash up to ROMless devices. It has a wide portfolio of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and more.

SH2A

The SH2A is essentially an upgrade to the SH2 core. It extends the compatibility of the SuperH family up to the 200 MHz performance. Announced in early 2008 was the first dual core SH2A device enhancing the performance of this popular family.

At launch in 2007 the SH2A bases SH7211 was the world's fastest embedded flash microcontroller running at 160 MHz. It has later been superseded by several newer SuperH devices running at up to 200 MHz.

New features on the SH2A core include:

  • Superscalar architecture: execution of 2 instructions simultaneously.
  • Harvard architecture with separate buses
    • Allows simultaneous instruction fetch and data access.
  • Two 5-stage pipelines.
  • 15 register banks for interrupt response in 6 cycles.
  • FPU option

The SH2A family today spans a wide memory field from 256k up to and includes many ROMless variations. The devices feature standard peripherals such as CAN, Ethernet, USB, LCD controllers, and many more as well as more application specific peripherals such as motor control timers, TFT controllers and peripherals dedicated to automotive powertrain applications.

Distinctions

  • Scalability
  • Cost efficient
  • Optimised for embedded applications
  • High performance

Tools

RSK Renesas Starter Kit

Several Modern Day SuperH devices are available with a Renesas Starter Kit. The RSKs have been designed to allow easy access to all on chip peripherals and includes a debug LCD panel.

To complete the RSK, Renesas has included the "E10A for starter kits" or the "E8A" on chip debugger, 60 day (256K code size limited) trial compiler. This makes the RSK one of the most comprehensive and complete evaluation / development systems in its class.

Debuggers

RTOS

One of the key advantages of the SuperH is that is supported by so many operating systems. Below is a selection of some of the RTOSs that are available for the SuperH

External links

Linux for SuperH

Linux distributions for SuperH

NetBSD on SuperH

OpenBSD on SuperH

v • d • e
RISC-based processor architectures






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