The Zilog Z80 is an 8-bit microprocessor designed and sold by Zilog from July 1976 onwards. It was widely used both in desktop and embedded computer designs as well as for military purposes. The Z80 and its derivatives and clones make up one of the most commonly used CPU families of all time, and, along with the MOS Technology 6502 family, dominated the 8-bit microcomputer market from the late 1970s to the mid-1980s.
Although Zilog made early attempts with advanced mini-computer like versions of the Z80-architecture (Z800 and Z280), these chips never caught on. The company was also trying hard in the workstation market with its Z8000 and 32-bit Z80000 (both unrelated to Z80). In recent decades Zilog has refocused on the ever-growing market for embedded systems (for which the original Z80 and the Z180 were designed) and the most recent Z80-compatible microcontroller family, the fully pipelined 24-bit eZ80 with a linear 16 MB address range, has been successfully introduced alongside the simpler Z180 and Z80 products.
Zilog licensed the Z80 core to any company wishing to make the device royalty free, though many East European and Russian manufacturers made unlicensed copies. This enabled a small company's product to gain acceptance in the world market since second sources from far larger companies such as Toshiba started to manufacture the device. Consequently Zilog has made less than 50% of the Z80s since its conception.
The Z80 came about when Federico Faggin, after working on the 8080, left Intel at the end of 1974 to found Zilog with Ralph Ungermann, and by July 1976 they had the Z80 on the market. It was designed to be binary compatible with the Intel 8080 so that most 8080 code, notably the CP/M operating system, would run unmodified on it.
The Z80 offered many real improvements over the 8080:
The Z80 quickly took over from the 8080 in the market, and became one of the most popular 8-bit CPUs. Perhaps a key to the success of the Z80 was the built-in DRAM refresh, and other features which allowed systems to be built with fewer support chips.
For the original NMOS design, the specified upper clock frequency limit increased successively from the introductory 2.5 MHz, via the well known 4 MHz, up to 6 and 8 MHz. A CMOS version was also developed with specified frequency limits[1] ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS version also allowed a low-power sleep with internal state retained (having no lower frequency limit).[2] The fully compatible derivatives Z180 and eZ80 are currently specified for up to 33 and 50 MHz respectively.
The programming model and register set are conventional and similar to many other processors, such as the related x86 family. The 8080 compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80, where the processor can quickly switch from one bank to the other; a feature useful for speeding up responses to single level, high priority interrupts. This feature was present in the Datapoint 2200 but was not implemented by Intel in the 8008. The dual-register set makes sense as the Z80 (like most microprocessors at the time) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers.[3] It also turned out to be quite useful for hard-optimized manual assembly coding. Some software, especially games for the ZX Spectrum took Z80 assembly optimization to rather extreme levels, employing the duplicated registers among other things.
The 8080 compatible registers:
Registers introduced with the Z80:
There is no direct access to the alternate registers, instead two special instructions, EX AF,AF' and EXX, each toggles one of two multiplexer flipflops; this enables fast context switches for interrupt service routines: EX AF, AF' may be used alone (for really simple and fast interrupt routines) or together with EXX to swap the whole AF, BC, DE, HL set; still much faster than pushing the same registers on the stack (slower, lower priority, or multi level interrupts normally use the stack to store registers).
The refresh register, R, increments[4] each time the CPU fetches an opcode (or opcode prefix) and has therefore no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; a famous example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6).
The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the im 2 instruction). It supplies the base address for a 128-entry table of service routine addresses which are selected via a pointer sent to the CPU during an interrupt acknowledge cycle. The pointer identifies a particular peripheral chip and/or peripheral function or event, where the chips are normally connected in a so called daisy-chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively.
The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the added addressing possibilities in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible; the 8008 actually was binary compatible with the Datapoint 2200 however).
In this process, the mnemonic L, for LOAD, was replaced by various abbreviations of the words LOAD, STORE and MOVE, intermixed with other symbolic letters. The mnemonic letter M, for memory (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestanding operand, while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H etc), within the instruction mnemonic itself (LDA, LHLD etc), or both at the same time (LDAX B, STAX D etc).
Datapoint 2200 & i8008 i8080 Z80 i8086/i8088 (ca -1973) (ca 1974) (1976) (1978) LBC MOV B,C LD B,C MOV BL,CL -- LDAX B LD A,(BC) MOV AL,[BX] LAM MOV A,M LD A,(HL) MOV AL,[BP] LBM MOV B,M LD B,(HL) MOV BL,[BP] -- STAX D LD (DE),A MOV [DX],AL LMA MOV M,A LD (HL),A MOV [BP],AL LMC MOV M,C LD (HL),C MOV [BP],CL LDI 56 MVI D,56 LD D,56 MOV DL,56 LMI 56 MVI M,56 LD (HL),56 MOV byte ptr [BP],56 -- LDA 1234 LD A,(1234) MOV AL,[1234] -- STA 1234 LD (1234),A MOV [1234],AL -- -- LD B,(IX+56) MOV BL,[SI+56] -- -- LD (IX+56),C MOV [SI+56],CL -- -- LD (IY+56),78 MOV byte ptr [DI+56],78 -- LXI B,1234 LD BC,1234 MOV BX,1234 -- LXI H,1234 LD HL,1234 MOV BP,1234 -- SHLD 1234 LD (1234),HL MOV [1234],BP -- LHLD 1234 LD HL,(1234) MOV BP,[1234] -- -- LD BC,(1234) MOV BX,[1234] -- -- LD IX,(1234) MOV SI,[1234]
Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions.
According to Masatoshi Shima, certain people within Zilog wanted a "computer oriented" image for the company, and also felt they needed to "differentiate" their first product from the 8080. Intel had also claimed copyright on their assembly mnemonics. Yet another assembly syntax was therefore developed, but this time with a more systematic approach:
These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,(1234) above.
It is interesting to see the resemblance between Z80 and 8086 syntax, as illustrated by the table. Apart from naming differences, and despite a certain discrepancy in basic register structure, the two are virtually isomorphous for a large portion of instructions. Whether this is due to some common influence on both design teams (above 8080, such as PDP-11), the competitive nature of the relation between the two designs, or maybe just a matter of taste, is, so far, uncertain.[5]
The Z80 uses 252 out of the available 256 codes as single byte opcodes; the four remaining codes are used extensively as opcode prefixes: CB and ED enable extra instructions and DD or FD selects IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; ZiLOG categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080 (allowing operation of 8080 programs on a Z80). The ZiLOG documentation further groups instructions into the following categories:
The bit set, reset, and test instructions are well adapted to I/O control. No multiply instruction is available in the original Z80. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because the flag-influencing properties of the 8080 had to be copied for compatibility. Load instructions do not affect the flags (except for the special purpose I and R register loads). The index register instructions are useful for reducing code size, and, while some of them are not much faster than "equivalent" sequences of simpler operations, they also save execution time indirectly by reducing the need to save and restore registers.[6] Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80; nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage.[7]
The index registers, IX and IY, were intended as flexible 16 bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16 bit only. In reality, they were implemented as a sort of copy of the HL register which is accessible as 16 bits or as a pair of 8 bit pair registers (H and L). Even the binary opcodes (machine language) were identical, but preceded by a new opcode prefix, as mentioned above. ZiLOG published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. As an example, the opcode 26h followed by an immediate byte value (LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value.
There are several other undocumented instructions as well.
As in all microprocessors, each instruction is divided into several steps which are usually termed machine cycles (M-cycles). Z80 needs between one and six M-cycles to execute a particular instruction as each M-cycle corresponds roughly to one memory access and/or internal operation. Many instructions actually end during the M1 of the next instruction which is known as a fetch/execute overlap.
Examples of typical instructions (R=read, W=write)
Total M-cycles instruction M1 M2 M3 M4 M5 M6 1 INC BC opcode 2 ADD A,100 opcode 100 3 ADD HL,DE opcode internal internal 4 SET 5,(HL) prefix opcode R(HL), set W(HL) 5 LD (IX+102),103 prefix opcode 102 103,add W(IX+102) 6 INC (IY+104) prefix opcode 104 add R(IY+104),inc W(IY+104)
The Z80 machine cycles are sequenced by an internal state machine which builds each M-cycle out of 3,4,5 or 6 discrete steps (i.e. clock cycles) depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. Naturally, it also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2-3 times higher). It does not imply tighter requirements on memory access times however, as a high resolution clock allows more precise control of memory timings and memory therefore can be active in parallel with the CPU to a greater extent (i.e. sitting less idle), allowing more efficient use of available memory performance. For instruction execution, the Z80 combines two full clock cycles into a long memory access period (the M1-signal) which would typically last only a fraction of a (longer) clock cycle in a more asynchronous design (such as the 6800, or similar).
Memory, especially EPROM, but also Flash, were generally slow as compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding SRAM; cacheless single cycle designs such as the eZ80 have therefore become much more meaningful recently.
Zilog introduced a number of peripheral parts for the Z80, which all supported the Z80's interrupt handling system and I/O address space. These included the CTC (Counter-Timer-Circuit), the SIO (Serial Input Output), the DMA (Direct Memory Access), the PIO (Parallel Input-Output) and the DART (Dual Asynchronous Receiver Transmitter). As the product line developed, low-power, high-speed and CMOS versions of these chips were produced.
In the same manner as the x86 family, but unlike contemporary 8-bit processors, like the Motorola 6800 and Mos Technology 6502, the Z80 and 8080 had a separate control line and address space for I/O instructions. While some Z80-based computers used "Motorola-style" memory mapped input/output devices, usually the I/O space was used to address one of the many Zilog peripheral chips compatible with the Z80. Zilog I/O chips supported the Z80's new mode 2 interrupts (see description above) which simplified interrupt handling for large numbers of peripherals.
The Z80 was officially described as supporting 16 bit (64 KB) memory addressing, and 8 bit (256 ports) I/O-addressing. Looking carefully at the hardware reference manual, it can be seen that several I/O instructions, OUT (C),A for example, assert the contents of the entire 16 bit BC register to the address bus. A design could choose to decode the entire 16 bit address bus on I/O operations in order to take advantage of this feature, though the code must then avoid the use of I/O instructions which do not send a 16 bit address. This feature has also been used to minimise decoding hardware requirements, such as in the Amstrad CPC and ZX81.
Mostek MK3880 and SGS-Thomson Z8400 (now ST Microelectronics) were both second-sources for the Z80. Sharp and NEC developed clones in NMOS, the LH-0080 and µPD780C respectively. Toshiba made a CMOS-version, the TMPZ84C00, which is believed (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z80-chips marked GoldStar and LG.
In East Germany, an unlicensed clone of the Z80, known as the U880, was manufactured. It was very popular and was used in Robotron's and VEB Mikroelektronik Mühlhausen's computer systems (e.g. the KC85-series) and also in many self-made computer systems (ex. COMP JU+TER). In Romania another unlicensed clone could be found, named MMN80CPU and produced by Microelectronica, used in home computers like TIM-S, HC, COBRA.
Also, several fully compatible clones of Z80 were created in the Soviet Union, notable ones being the T34BM1, also called КP1858ВМ1. The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in late 80s, there are much more T34BM1's than КP1858ВМ1's. This CPUs are not full 'clones' of the Z80, they have different behaviour in some situations. They are said to be made for Soviet ZX Spectrum clones, due to their correct work in these computers. Another Soviet CPU, the КP580ИK80 (later marked as КP580ВМ80), was a clone of the Z80's predecessor, the Intel 8080.
Fully compatible with the original Z80:
Non, or partially, compatible:
No longer produced:
A commercial, functionally equivalent, CPU core is the Evatronix CZ80CPU, available as synthesizable VHDL or Verilog source code, for high volume ASICs, or as post-synthesis EDIF netlists, for low volume FPGAs from Actel, Altera, Lattice or Xilinx.
Free versions are the T80 and TV80, available as VHDL and Verilog sources under a BSD style license. The VHDL version, once synthesized, can be clocked up to 35 MHz on a Xilinx Spartan II FPGA. For large production series, it's much cheaper to use a traditional solution (or ASIC) than an FPGA, however.
Software emulation of the Z80 instruction set on modern PCs runs faster than the original Z80 CPU ran and is used for home computer simulators (such as ZX Spectrum and Amstrad CPC) and also for video game emulators such as MAME, which executes 1980s vintage video games. SIMH emulates MITS Altair 8800 computer with Intel 8080, Zilog Z80 or Intel 8086 processors.
During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the CP/M operating system; a CPU/OS combination that dominated the market in much the same way that Windows based Intel-machines do today. Two well-known examples of Z80+CP/M business computers are the portable Osborne 1 and the Kaypro series. Research Machines manufactured the 380Z and 480Z microcomputers which were networked with a thin Ethernet type LAN and CP/NET in 1981. Other manufacturers of such systems included Televideo, Xerox and a number of more obscure firms. Some systems used multi-tasking operating system software to share the one processor between several concurrent users.
Home computers using the Z80 (or equivalent) include the following:
For a comprehensive overview, see the List of home computers using the Z80.
The Zilog Z80 has long been a popular microprocessor in embedded systems and microcontroller cores, where it remains in widespread use today. The following list provides examples of such applications of the Z80, including uses in consumer electronics products.
Industrial/professional:
Consumer electronics:
Musical instruments etc:
Zilog Components Data Book, Zilog, Campbell California, 1985, no ISBN
|
||||||||||||||
|
|||||
Why are we here?
All text is available under the terms of the GNU Free Documentation License
This page is cache of Wikipedia. History